import V3_parameter::*;

module V3 
(

//input/output data for task2

input wire a,b,
					
output wire	c,

//input/output data for task3

input wire d, clk, reset,

output reg out,

//input/output data for task4

input wire [P_input-1:0] A,
input wire [P_input-1:0] B,
input wire [P_input-1:0] C,

output reg [P_output-1:0] DATA_OUT);

//------------------------------------

reg [P_output-1:0] multiplication;

reg [P_output-1:0] save_C;
reg [P_output-1:0] save_2C;
  
  
//------------------------------------
//task2

	assign c = a * b;
	
//------------------------------------  
//task3

always @(negedge reset or posedge clk)
begin
	if (!reset)
		out<= 0;
	else
		out<= d;
end

//------------------------------------
//task4

always @(negedge reset or posedge clk)
begin
	if (!reset)
		begin
			DATA_OUT<= 0;
			multiplication <= 0;
			save_C <= 0;
			save_2C <= 0;
		end
	else
		begin
			multiplication <= A * B;
			save_C <= C;
			save_2C <= save_C;
			DATA_OUT <= multiplication + save_2C;
			end
end

//------------------------------------
endmodule	